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MF1511-03
S1D15714 Series
Rev. 1.0
NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notics. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no repersesnation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. (c)SEIKO EPSON CORPORATION 2003, All rights reserved.
Rev. 1.0
SED1575 Series
Contents
1. DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. BLOCK DIAGRAM ............................................................................................................................................. 2 4. PIN ASSIGNMENT ............................................................................................................................................ 3 5. PIN DESCRIPTION ........................................................................................................................................... 7 6. FUNCTIONAL DESCRIPTION ........................................................................................................................ 11 7. COMMAND ...................................................................................................................................................... 26 8. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 45 9. DC CHARACTERISTICS ................................................................................................................................. 46 10. TIMING CHARACTERISTICS ......................................................................................................................... 53 11. MPU INTERFACE ........................................................................................................................................... 58 12. CONNECTION BETWEEN LCD DRIVERS ..................................................................................................... 59 13. LCD PANEL WIRING ...................................................................................................................................... 60 14. CAUTIONS ...................................................................................................................................................... 61
-i-
Rev. 1.0
S1D15714 Series
1. DESCRIPTION
The S1D15714 Series is a single chip MLS driver for dot matrix liquid crystal displays which can be directly connected to the microcomputer bus. It accepts the 8bit parallel or serial display data from the microcomputer to store the data in the on-chip display data RAM, and issues liquid crystal drive signals independently of the microcomputer. The S1D15714 Series incorporates a display data RAM (65 x 168 bits), 1 bit of the on-chip RAM respond to one-dot pixels. The S1D15714 Series features 65 common output circuits and 168 segment output circuits. A single chip provides a display of 10 characters by 4 lines with 65 x 168 dots (16 x 16 dots) and display of 14 characters by 5 lines by the 12 x 12 dot-character font. The S1D15714 Series incorporates the analog temperature sensor circuit that changes output voltage depending on ambient temperature and can be used to constitute a system to provide optimum LCD contrast throughout a wide temperature range without need for use of supplementary parts such as the thermistor, under controls of a micro computer. Display data RAM read/write operations do not require operation clock from outside, thereby ensuring operation with the minimum current consumption. Furthermore, it incorporates a LCD-drive power supply characterized by low power consumption and a CR oscillator circuit for display clock; therefore, the display system of a handy and high-performance instrument can be realized by use of the minimum current consumption and minimum chip configuration.
2. FEATURES
* Direct RAM data display by display data RAM Normally white display is in normal mode RAM bit data "1" : On and black "0" : Off and white * RAM capacity 65 x 168 = 10,920 bits * Liquid crystal drive circuit 65 common outputs and 168 segment outputs * High-speed 8-bit MPU interface (directly connectable to the MPUs of both 80/68 series) /serial interface possible * A variety of command functions n-line reversal, display data RAM address control, display ON/OFF, display normal/reverse rotation, display all lighting ON/OFF, liquid crystal drive power supply circuit control, display clock built-in oscillator circuit control * MLS drive technology Built-in high precision voltage regulation function * High precision CR oscillator circuit incorporated * Low power consumption * Built-in temperature sensor circuit * Power supply Logic power supply 1: VDI - VSS = 2.7 V to 3.3 V Logic power supply 2: VDD - VSS = 2.7 V to 5.5 V Liquid crystal drive power supply: V3 - VSS = 5.6 to 16.2 V Boosting power supply: VDD2 - VSS = VDD to 5.5 V * Wide operation temperature range: -40 to 85C * CMOS process * Shipping form : Bare chips * Light and radiation proof measures are not taken in designing.
Series specifications
Product name S1D15714D00B000 Form of shipping Bare chip Chip thickness 0.625mm
Rev. 1.0
EPSON
1
S1D15714 Series
3. BLOCK DIAGRAM
SEG167
COM63
VDD2 VDD VSS
V3 V2 V1 VC MV1 MV2 MV3 (VSS) SEG Drivers COM Drivers
Decode circuit
COMS
COMS
COM0
SEG0
Temperature sensor circuit
SVD2 SV22
Display data latch circuit CAP1+
Power supply circuit Display timing generator circuit
CAP1- CAP2+ CAP2- VOUT CAP3+ CAP4+ CAP5+
FR SYNC F1 F2 CL DOF M/S
Page address
Display data RAM 168 x 65
VDI
Column address
Oscillator circuit
Line address
I/O buffer
CLS
Bus holder
Command decoder
Status
MPU Interface
D6 (SCL)
WR (R/W)
D7 (SI)
TEST1
RD (E)
2
EPSON
TEST
RES
C86
P/S
CS
D5
D4
D3
D2
D1
D0
A0
Rev. 1.0
S1D15714 Series
4. PIN ASSIGNMENT
4.1 Chip Assignment
91 92 1 Alignment Mark1
S1D15714 Series
(0, 0)
Y X
333
126 127 Alignment Mark2 298
299 Die No.
D157ED0B
Item Chip size Chip thickness Bump pitch Bump size PAD No.1, 2, 13, 16, 29, 91 PAD No.3 to 12, 14, 15, 17 to 28, 30 to 90 PAD No.92 to 126, 299 to 333 PAD No.127 to 298 Bump height
Size X 11.20 x 0.625 51 (Min.) 36 x 84 81 x 84 85 x 34 42 x 85 17 (Typ.) Y 2.27
Unit mm mm m m m m m m
4.2 Alignment mark
Alignment coordinate 1 (5364, 975) m 2 (-5415, -942) m Mark size a = 70.5 m b = 20.3 m c = 79.5 m
a
b
c
Rev. 1.0
EPSON
3
S1D15714 Series 4.3 Pad Center Coordinates
Unit: m PAD Pin No. Name 1 NC 2 VDD 3 TEST1 4 SYNC 5 FR 6 CL 7 DOF 8 F1 9 F2 10 CS 11 RES 12 A0 13 VSS 14 WR,R/W 15 RD,E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D6, SCL 25 D7, SI 26 D7, SI 27 VDI 28 VDI 29 VDD 30 M/S 31 CLS 32 VSS 33 VSS 34 VSS 35 VSS 36 TEST 37 C86 38 P/S 39 VDD 40 VDD 41 VDD 42 VDD 43 VDD2 44 VDD2 45 VDD2 46 VDD2 47 VOUT 48 VOUT 49 VOUT 50 CAP1+ X 4986 4935 4856 4750 4643 4537 4430 4324 4217 4111 4004 3898 3819 3740 3634 3555 3476 3370 3263 3157 3050 2944 2837 2731 2624 2518 2411 2305 2226 2147 2041 1934 1828 1721 1615 1508 1402 1295 1189 1082 976 869 763 656 550 443 -302 -409 -515 -622 Y 982 PAD No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name CAP1+ CAP1+ CAP1- CAP1- CAP1- CAP3+ CAP3+ CAP3+ CAP5+ CAP5+ CAP5+ VOUT CAP4+ CAP4+ CAP4+ CAP2- CAP2- CAP2- CAP2+ CAP2+ CAP2+ V3 V3 V2 V2 V1 V1 VC VC MV1 MV1 MV2 MV2 VSS VSS VSS VDD NC SVD2 SV22 NC NC COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 X -728 -835 -941 -1048 -1154 -1261 -1367 -1474 -1580 -1687 -1793 -1900 -2006 -2113 -2219 -2326 -2432 -2539 -2645 -2752 -2858 -2965 -3071 -3178 -3284 -3391 -3497 -3604 -3710 -3817 -3923 -4030 -4136 -4243 -4349 -4456 -4562 -4669 -4775 -4882 -4961 -5449 Y 982 PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Pin Name COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS NC NC NC SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X -5449 Y 463 412 361 310 259 208 157 106 55 4 -47 -98 -149 -200 -251 -302 -353 -404 -455 -506 -557 -608 -659 -710 -761 -812 -982
922 871 820 769 718 667 616 565 514
-5130 -5070 -5010 -4950 -4890 -4830 -4770 -4710 -4650 -4590 -4530 -4470 -4410 -4350 -4290 -4230 -4170 -4110 -4050 -3990 -3930 -3870 -3810 -3750
4
EPSON
Rev. 1.0
S1D15714 Series
Unit: m PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pin Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 X -3690 -3630 -3570 -3510 -3450 -3390 -3330 -3270 -3210 -3150 -3090 -3030 -2970 -2910 -2850 -2790 -2730 -2670 -2610 -2550 -2490 -2430 -2370 -2310 -2250 -2190 -2130 -2070 -2010 -1950 -1890 -1830 -1770 -1710 -1650 -1590 -1530 -1470 -1410 -1350 -1290 -1230 -1170 -1110 -1050 -990 -930 -870 -810 -750 Y -982 PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Pin Name SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 X -690 -630 -570 -510 -450 -390 -330 -270 -210 -150 -90 -30 30 90 150 210 270 330 390 450 510 570 630 690 750 810 870 930 990 1050 1110 1170 1230 1290 1350 1410 1470 1530 1590 1650 1710 1770 1830 1890 1950 2010 2070 2130 2190 2250 Y -982 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Pin Name SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 SEG166 SEG167 NC NC NC COM32 X 2310 2370 2430 2490 2550 2610 2670 2730 2790 2850 2910 2970 3030 3090 3150 3210 3270 3330 3390 3450 3510 3570 3630 3690 3750 3810 3870 3930 3990 4050 4110 4170 4230 4290 4350 4410 4470 4530 4590 4650 4710 4770 4830 4890 4950 5010 5070 5130 5449 Y -982
-812 -761
Rev. 1.0
EPSON
5
S1D15714 Series
Unit: m PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 Pin Name COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS NC X 5449 Y -710 -659 -608 -557 -506 -455 -404 -353 -302 -251 -200 -149 -98 -47 4 55 106 157 208 259 310 361 412 463 514 565 616 667 718 769 820 871 922
6
EPSON
Rev. 1.0
S1D15714 Series
5. PIN DESCRIPTION
5.1 Power Pin
Pin name VDD VSS VDD2 VDI I/O Power supply Power supply Power supply Power supply Description Connect to system MPU power supply pin VCC. Connect to the system GND. MV3 is short circuited with MV3 inside the IC chip. Boosting power supply circuit. It is necessary to maintain the co-relation between the VDD2 and VDD as: VDD2 VDD. This is the power supply pin for operating internal circuits that are generated from VDD. Connect a capacitor for stabilizing voltage between VDI and VSS. VDI can be used for external inputs as well. In case of external input, make TEST1 = LOW and use this pin in the ranges of 3.3V VDI 2.7V and VDD VDI. When using it in the range of VDD = 2.7 to 3.3V, make TEST1 = LOW and short-circuit this pin to VDD. A liquid crystal drive multi-level power supply. The voltages determined by the liquid crystal cell are impedance-converted by resistive divider and operational amplifier for application. The following order must be maintained: V3 V2 V1 VC MV1 MV2 MV3 (=VSS) MV3 is short circuited with MV3 inside the IC chip. Master operation: When power supply is turned on, the following voltage is applied to each pin by the built-in power supply circuit. The voltage is selected by Bias Change Command. V2 V1 VC MV1 MV2 6/8*V3 5/8*V3 4/8*V3 3/8*V3 2/8*V3 16/20*V3 13/20*V3 10/20*V3 7/20*V3 4/20*V3 14/16*V3 11/16*V3 8/16*V3 5/16*V3 2/16*V3 Number of pins 8 8 4 2
V3, V2, V1, VC, MV1, MV2
Power supply
12 (2 each)
5.2 LCD Power Supply Circuit Pin
Pin name CAP1+ CAP1- CAP2+ CAP2- VOUT I/O O O O O I/O Description Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP1- pin. Pin connected to the negative side of the step-up capacitor. Connect the capacitor between this pin and CAP1+ pin. Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP2- pin. Pin connected to the negative side of the step-up capacitor. Connect the capacitor between this pin and CAP2+ pin. Output pin for step-up. Connect the capacitor between this pin and VDD or VDD2. When VOUT is used with external voltage, this pin can be a input terminal. Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP2- pin. Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP1- pin. Pin short circuited with VOUT terminal. When VOUT is used with external voltage, this pin can be left OPEN. Number of pins 3 3 3 3 4
CAP3+ CAP4+ CAP5+
O O O
3 3 3
Rev. 1.0
EPSON
7
S1D15714 Series 5.3 System Bus Connection Pin
Pin name D7 to D0 (SI) (SCL) I/O I/O Description Connects to the 8-bit or 16-bit MPU data bus via the 8-bit bi-directional data bus. When the serial interface is selected (P/S = LOW and C86 = LOW), D7 serves as the serial data input (SI) and D6 serves as the serial clock input (SCL), In this case, D0 through D5 go to a high impedance state. When the Chip select is inactive, D0 through D7 go to a high impedance state. Normally, the least significant bit MPU address bus is connected to distinguish between data and command. A0 = HIGH : indicates that D0 to D7 are display data or command parameters. A0 = LOW : indicates that D0 to D7 are control commands. When the RES is LOW, initialization is achieved. Resetting operation is done on the level of the RES signal. A chip select signal. When CS = LOW, signals are active, and data/command input/output are enabled. * When the 80 series MPU is connected. "Active" "LOW" A pin for connection of the RD signal of the 80 series MPU. When this signal is LOW, the data bus of the S1D15714 Series is in the output state. * When the 68 series MPU is connected. "Active" "HIGH" Serves as a 68 series MPU enable clock input pin. * When the 80 series MPU is connected. "Active" "LOW" A pin for connection of the WR signal of the 80 series MPU. Signals on the data bus are latched at the leading edge of the WR signal. * Serves as a read/write control signal input pin when the 68 series MPU is connected. R/W = HIGH : Read R/W = LOW : Write A MPU interface switching pin. C86 = HIGH : 68 series MPU interface C86 = LOW : 80 series MPU interface (Serial Interface) Parallel data input/serial data input select pin P/S = HIGH : Parallel data input P/S = LOW : Serial data input P/S = LOW and C86 = LOW : Serial interface spec P/S = LOW and C86 = HIGH : Please do not set up The following Table shows the summary: P/S C86 Data/Command A0 A0 Data D0 to D7 SI (D7) Read/Write Serial clock RD, WR Write only SCL (D6) Number of pins 10
A0
I
1
RES CS RD (E)
I I I
1 1 1
WR (R/W)
I
1
C86
I
1
P/S
I
1
HIGH LOW LOW LOW
When P/S = LOW, D0 to D5 are high impedance. D0 to D5 can be HIGH, LOW or open. RD(E) and WR(R/W) are locked to HIGH or LOW. The serial data input does not allow the RAM display data to be read.
8
EPSON
Rev. 1.0
S1D15714 Series
Number of pins 1
Pin name CLS
I/O I
Description A pin used to select Enable/Disable state of the built-in oscillator circuit for display clock. CLS = HIGH : Built-in oscillator circuit Enabled CLS = LOW : Built-in oscillator circuit Disabled (External input) When CLS is LOW, display clock is input from the CL pin. When the S1D15714 Series is used in the master/slave mode, each CLS pins must be set to the same level. Display clock Built-in oscillator circuit used External input Master HIGH LOW Slave HIGH LOW
M/S
I
A pin used to select the master/slave operation for S1D15714 Series. Liquid crystal display system is synchronized when the master operation outputs the timing signal required for liquid crystal display, while the slave operation inputs the timing signal required for liquid crystal display. M/S = HIGH : Master operation M/S = LOW : Slave operation The following Table shows the relation in conformance to the M/S and CLS: M/S HIGH CLS Oscillation circuit Enabled Disabled Disabled Disabled Power circuit Enabled Enabled Disabled Disabled FR, DOF, F1, F2, SYNC Output Output Input Output Input Input Input Input CL
1
HIGH LOW HIGH LOW LOW
CL
I/O
Display clock input/output pin. The following Table shows the relation in conformance to the M/S and CLS state: CLS HIGH HIGH LOW HIGH LOW LOW M/S CL Output Input Input Input
1
FR
I/O
F1, F2, SYNC
I/O
DOF
I/O
When you want to use the S1D15714 Series in the master/slave mode, connect each CL pin. A liquid crystal alternating current input/output pin. M/S = HIGH : Output M/S = LOW : Input When you want to use the S1D15714 Series in the master/slave mode, connect each FR pin. A liquid crystal sync signal input/output pin. M/S = HIGH : Output M/S = LOW : Input When you want to use the S1D15714 Series in the master/slave mode, connect each F1, F2 and SYNC pins. A liquid crystal blanking control pin. M/S = HIGH : Output M/S = LOW : Input When you want to use the S1D15714 Series in the master/slave mode, connect each DOF pin.
1
3 (1 each)
1
Rev. 1.0
EPSON
9
S1D15714 Series 5.4 Liquid crystal drive pin
Pin name SEG0 to SEG167 COM0 to COM63 COMS I/O O Description Liquid crystal segment drive output pins. One of the V2, V1, VC, MV1, and MV2 levels is selected by a combination of the display RAM content and FR/F1/F2 signals. Liquid crystal common drive output pins. One of the V3, VC, MV3 (VSS) levels is selected by a combination of the scan data and FR/F1/F2 signals. COM output pins for indicator. These pins outputted the same signal. Set to OPEN not used. When COMS is used for the master/ slave configuration, the same signal is output to both the master and slave. Number of pins 168
O
64
O
2
5.5 Temperature Sensor Pins
Pin name SVD2 SV22 I/O O O Description This is analog voltage output pin for the temperature sensor. This is test pin for the temperature sensor. Fix the pin OPEN. Number of pins 1 1
5.6 Test pins
Pin name TEST TEST1 I/O I I Description IC chip test pin. Fix the pin LOW. VDI generation circuit control pin. When using this pin in the range of VDD = 3.3 to 5.5V, fix this pin to HIGH. When using this pin in the range of VDD = 2.7 to 3.3V, fix this to LOW and short-circuit VDD to VDI. When this pin is used after TEST1 is switched from LOW to HIGH, the initialization to make Reset RES = LOW is required after TEST1 is switched to HIGH. The VDI generation circuit operates independently from power saving. To reduce the current consumption close to the static current with the power saving function while this pin is used in the range of VDD = 3.3 to 5.5V, make it possible to switch TEST1 to LOW during power saving. Number of pins 1 1
10
EPSON
Rev. 1.0
S1D15714 Series
6. FUNCTIONAL DESCRIPTION
6.1 MPU Interface
6.1.1 Selection of Interface Type S1D15714 Series allows data to be sent via the 8-bit bi-directional data buses (D7 to D0) or serial data input (SI). By setting the polarity of the P/S pin and C86 pin to HIGH or LOW, you can select either 8-bit parallel data input or serial data input, as shown in Table 6.1. Table 6.1 P/S HIGH LOW C86 -- Parallel input LOW Serial input CS CS CS A0 RD WR D7 D6 D5 to D0 A0 RD WR D7 D6 D5 to D0 A0 -- -- SI SCL (HZ) --: Fixed to HIGH or LOW HZ: High impedance state
6.1.2 Parallel interface When the parallel interface is selected (P/S = HIGH), direction connection to the MPU bus of either 80 series MPU or 68 series MPU is performed by setting the 86 pin to either HIGH or LOW, as shown in Table 6.2. Table 6.2 P/S HIGH : 68 series MPU bus LOW : 80 series MPU bus CS CS CS A0 A0 A0 RD E RD WR R/W WR D7 to D0 D7 to D0 D7 to D0
The data bus signals are identified by a combination of A0, RD (E), and WR (R/W) signals as shown in Table 6.3. Table 6.3 Common A0 1 1 0 68 series R/W 1 0 0 0 1 1 80 series RD WR 1 0 0 Function Display data read, status read Display data write, Command parameter write Command write
6.1.3 Serial interface When the serial interface is selected (P/S = LOW and C86 = LOW), the chip is active (CS = LOW and C86 = LOW), and reception of serial data input (SI) and serial clock input (SCL) is enabled. Serial interface comprises a 8-bit shift register and 3-bit counter. The serial data are latched by the rising edge of serial clock signals in the order of D7, D6, .... and D0 starting from the serial data input pin. On the rising edge of 8th serial clock signal, they are converted into 8-bit parallel data to be processed. Whether serial data input is a display data or command is identified by A0 input. A0 = HIGH indicates display data, while A0 = LOW shows command data. The A0 input is read and identified at every 8 x n-th rising edge of the serial clock after the chip has turned active. Fig. 6.1 shows the serial interface signal chart.
Rev. 1.0
EPSON
11
S1D15714 Series
CS SI SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
A0
Fig. 6.1 * When the chip is inactive, the counter is reset to the initials state. * Reading is not performed in the case of serial interface. * For the SCL signal, a sufficient care must be taken against terminal reflection of the wiring and external noise. Recommend to use an actual equipment to verify the operation. 6.1.4 Chip Selection The S1D15714 Series has chip select pin. MPU interface or serial interface is enabled only when CS = LOW. When the chip select pin is inactive, D0 to D5 are in the state of high impedance, while A0, RD and WR inputs are disabled. When serial interface is selected, the shift register and counter are reset. 6.1.5 Access to display data RAM and internal register Access to S1D15714 Series series viewed from the MPU side is enabled only if the cycle time requirements are kept. This does not required waiting time; hence, high-speed data transfer is allowed. Furthermore, at the time of data transfer with the MPU, S1D15714 Series provides a kind of inter-LSI pipe line processing via the bus holder accompanying the internal data bus. For example, when data is written to the display data RAM by the MPU, the data is once held by the bus holder. It is written to the display data RAM before the next data write cycle comes. On the other hand, when the MPU reads the content of the display data RAM, it is read in the first data read cycle (dummy), and the data is held in the bus holder. Then it is read onto on the system bus from the bus holder in the next data read cycle. Restrictions are imposed on the display data RAM read sequence. When the address has been set, specified address data is not output to the Read command immediately after that. The specified address data is output in the second data reading. This must be carefully noted. Therefore, one dummy read operation is mandatory subsequent to address setting or write cycle. Fig. 6.2 illustrates this relationship.
12
EPSON
Rev. 1.0
S1D15714 Series
Write
A0
MPU
WR DATA White
Latch N N+1 N+2
Internal timing
Command BUS Holder Write Signal N N+1 N+2
Read
A0 WR
MPU
RD DATA Read Command Dumy n n+1
Internal timing
Read Signal Column Address Bus Holder Preset N Read command code Increment N+1 n n+1 N+2 n+2
Dummy Read
Data Read
Data Read
Fig. 6.2
6.2 Display data RAM
6.2.1 Display Data RAM This is a RAM to store the display dot data, and comprises 65 x 168 bits. Access to the desired bit is enabled by specifying the page address and column address. The RAM 1 bit built in the one-dot pixel responds to it. When the RAM bit data is "1", the display is black. If it is "0", the display is given in white. RAM bit data "1" : Light On Black (when display is in normal mode) "0" : Light Off White (when display is in normal mode)
Rev. 1.0
EPSON
13
S1D15714 Series
Display data D7 to D0 from the MPU correspond to LCD common direction, as shown in Fig. 6.3 and 6.4. Therefore, less restrictions when multi-chip usage. Furthermore, read/write operations from the MPU to the RAM are carried out via the input/output buffer. The read operation from Display data RAM is designed as an independent operation. Accordingly, even if the MPU accesses the RAM asynchronously during LCD display, no adverse effect is given to display.
D0 D1 D2 D3 D4 0111 1000 0000 0111 1000 0 0 0 0 0 COM0 COM1 COM2 COM3 COM4
Display data RAM
LCD
Fig. 6.3 Binary
6.2.2 Page address circuit/column address circuit The address of the display data RAM to be accessed is specified by the Page Address Set command and Column Address Set command, as shown in Fig. 6.4. For Address incremental direction, either the column direction or page direction can be selected by the Address Direction command. Whichever direction is chosen, increment is carried out by positive one (+1) after write or read operation. When the column direction is selected for address increment, the column address is increased by +1 for every write or read operation. After the column address has accessed up to A7H, the page address is incremented by +1 and the column address shifts to 0H. When the page direction is selected for address increment, the page address is increased with the column address locked in position. When the page address has accessed up to Page 8, the column address is incremented by +1, and the page address goes to Page 0. Whichever direction is selected for address increment, the page address goes back to Page 0 and the column address to 0H after access up to the column address A7H of page address Page 8. As shown in Fig. 6.4, relationship between the display data RAM column address and segment output can be reversed by the Column Address Set Direction command. This will reduce restrictions on IC layout during LCD module assembling. Page 8 is a RAM domain only for indicators, only D0 of its display data is effective. Table 6.4 SEG output ADC "0" (D0) "1" SEG0 SEG167 0(H) Column Address A7(H) A7(H) Column Address 0(H)
6.2.3 Line address circuit The line address circuit specifies the line address corresponding to COM output when the contents of the display data RAM is displayed, as shown in Fig. 6.4. Normally, the top line of the display (COM0 output in the case of normal rotation of the common output status and COM63 output in the case of reverse rotation) is specified by the Display Start Line Address Set command. The display area starts from the specified display start line address to cover the area corresponding to the lines specified by the DUTY Set command in the direction where the line address increments. If the display start line address set command is used for dynamic modification of the line address, screen scroll and page change are enabled. 6.2.4 Display data latch circuit The display data latch circuit is a latch to temporarily latch the display data output from then display data RAM to the liquid crystal drive circuit. Display normal/reverse, display ON/OFF, and display all lighting ON/OFF commands control the data in this latch, without the data in the display data RAM being controlled. 14
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Rev. 1.0
S1D15714 Series
Page Address D3 D2 D1 D0 Line When the display start line is set to 1CH Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 10 D0 D0 ADC A0 A1 A2 A3 A4 A5 A6 A7 Common Output state: Normal rotation COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 Column Address 00 01 02 03 04 05 06 07
A7 A6 A5 A4 A3 A2 A1 A0
SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 SEG166 SEG167
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
07 06 05 04 03 02 01 00
LCD
Fig. 6.4 Binary display Rev. 1.0
EPSON
Out
64 lines
15
S1D15714 Series 6.3 Oscillator circuit
A display clock is generated by the CR oscillator. The oscillator circuit is enabled only when M/S = HIGH and CLS = HIGH. Oscillation starts after input of the built-in oscillator circuit ON command input. When CLS = LOW, oscillation stops, and display clock is input from the CL pin.
6.4 Display timing generation circuit
Timing signals are generated from the display clock to the line address circuit and display data latch circuit. Synchronized with display clock, display data is latched in display data latch circuit, and is output to the segment drive output pin. Reading of the display data into the LCD drive circuit is completely independent of access from the MPU to the display data RAM. Accordingly, asynchronous access to the display data RAM during LCD display does not give any adverse effect; like as flicker. Furthermore, the display clock generates internal common timing, liquid crystal alternating signal(FR), field start signal (SYNC) and drive pattern signal (Fl and F2). The FR normally generates 2-frame alternating drive system drive waveform to the liquid crystal drive circuit. The n-line reverse alternating drive waveform is generated for each 4 x (a+1) line by setting data on the n-line reverse drive register. When there is a display quality problem including crosstalk,the problem may be solved using the n-line reverse alternating drive. Execute liquid crystal display to determine the number of lines "n" for alternation. When you want to use the S1D15714 Series in multi-chip configuration, supply display timing signal (FR, SYNC, F1, F2, CL, DOF) to the slave side from the master side. Table 6.5 shows the statuses of FR, SYNC, F1, F2, CL, DOF. Table 6.5 Operating mode Master (M/S = HIGH) Built-in oscillator circuit enabled (CLS = HIGH) Built-in oscillator circuit disabled (CLS = LOW) Slave (M/S = LOW) Built-in oscillator circuit enabled (CLS = HIGH) Built-in oscillator circuit disabled (CLS = LOW) CL Output Input Input Input FR,SYNC, F1, F2, DOF Output Output Input Input
6.5 Liquid crystal drive circuit
6.5.1 SEG Drivers This is a SEG output circuit. It selects the five values of V2, V1, VC, MV1 and MV2 using the driver control signal determined by the decoder, and output them. 6.5.2 COM Drivers This is a COM output circuit. It selects three values of V3, VC and MV3(VSS) using the driver control signal determined by the decoder, and output them. S1D15714 Series allows the COM output scanning direction to be set by the common output status select command. (See Table 6.6). This will reduce restrictions on IC layout during LCD module assembling. Table 6.6 Status Normal Reverse Direction of COM scanning COM 0 COM63 COM63 COM 0
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Rev. 1.0
S1D15714 Series 6.6 Power supply circuit
This is a power supply circuit to generate voltage required for liquid crystal drive, and is characterized by a low power consumption. It consists of a step-up circuit, voltage regulating circuit and liquid crystal drive voltage generating circuit, and is enabled only during master operation. The power supply circuit uses the power control set command to provide an on/off control of step-up circuit, voltage regulating circuit and liquid crystal drive potential generating circuit. This allows a combined use of the external power supply and part of built-in power supply functions. Table 6.7 shows functions controlled by the 3-bit data of the control set command, and Table 6.8 shows reference combinations. Also, by use of the magnification of amplification changing over command, it is possible to select the amplifying magnification from five different steps. The power supply circuit is enabled only during master operation.
Table 6.7 Respective Bit Control Contents by Power Control Set Command Item D2 Boosting circuit control bit D1 Voltage regulator circuit (V3 regulator circuit) control bit D0 LCD driving potential generating circuit (LCDV circuit) control bit "1" ON ON ON State "0" OFF OFF OFF
Table 6.8 Reference combination Circuits used 1 Use of all built-in power supplies 2 V3 regulating circuit and LCDV circuit only 3 LCDV circuit only 4 External power supply only D2 D1 D0 Boosting VC regulator circuit circuit "1" "1" 111 0 0 0 1 0 0 1 1 0 x "0" x "0" x "0" "1" x "0" x "0" LCDV circuit "1" "1" "1" x "0" Eternal input power supply -- VOUT V3 V3, V2, V1, VC, MV1, MV2
* Any combinations other than the above are not available. The V3 voltage is generated from VOUT. To use the circuit as shown in 2 in the above table, input the voltage, which makes VOUT V3+0.2V, from the VOUT pin.
Rev. 1.0
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S1D15714 Series
6.6.1 Amplification circuit By use of the amplification circuit being built into the S1D15714 Series, it is possible to make amplification of the electric potential between VDD2-VSS onto quintuple amplification, quadruple amplification, triple amplification or double amplification. Also, by use of the relevant command, it is possible to select either one from the quintuple amplification, quadruple amplification, triple amplification, double amplification and equal amplification. 1 When using the quintuple-boosting, connect the capacitor C1 between CAP1+ <-> CAP1-, between CAP2+ <-> CAP2-, between CAP3+ <-> CAP1-, between CAP4+ <-> CAP2-, between VDD2 <-> VOUT and short-circuit the CAP5+, CAP4+ and VOUT pin before use. 2 When using the quadruple-boosting, connect the capacitor C1 between CAP1+ <-> CAP1-, between CAP2+ <-> CAP2-, between CAP3+ <-> CAP1- and between VDD2 <-> VOUT and short-circuit the CAP5+, CAP4+ pin and the VOUT pin before use. 3 When using the triple-boosting, connect the capacitor C1 between CAP1+ <-> CAP1-, between CAP2+ <-> CAP2- and between VDD2 <-> VOUT and short-circuit the CAP5+, CAP4+ pin, CAP3+ pin and the VOUT pin before use. 4 When using the double-boosting, connect the capacitor C1 between CAP1+ <-> CAP1- and between VDD2 <-> VOUT, open the CAP2- pin and short-circuit the CAP5+, CAP4+ pin, CAP3+ pin, CAP2+ pin and the VOUT pin before use.
VDD2 C1 + C1 C1 + VOUT CAP1+ C1 C1 C1 + +
VDD2 C1 VOUT CAP1+ C1 + +
VDD2 C1 VOUT CAP1+ C1 + +
VDD2 VOUT CAP1+ CAP1- CAP3+ CAP5+ CAP4+ OPEN CAP2- CAP2+
S1D15714 Series
S1D15714 Series
S1D15714 Series
CAP1- + CAP3+ CAP5+
CAP1- + CAP3+ CAP5+ CAP4+
CAP1- CAP3+ CAP5+ CAP4+ C1 + CAP2- CAP2+
C1 C1
+
CAP4+ CAP2-
+
C1 +
CAP2- CAP2+
CAP2+
1 Quintuple-boosting
2 Quadruple-boosting
3 Triple-boosting
4 Double-boosting
Fig. 6.5 below shows the electric potential relations when making respective amplifications.
VOUT = 5 x VDD2 = 15V VOUT = 4 x VDD2 = 12V VOUT = 3 x VDD2 = 12V VOUT = 2 x VDD2 = 10V
VDD2 = 5V VDD2 = 3V VSS = 0V VDD2 = 3V VSS = 0V VDD2 = 4V VSS = 0V VSS = 0V
Electric potential relations when making the quintuple amplification
Electric potential relations Electric potential relations when making the quadruple when making the triple amplification amplification
Electric potential relations when making the double amplification
Fig. 6.5 * Set the voltage range of the VDD2 so that the voltage of the VOUT pin may not exceed the absolute maximum rating.
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S1D15714 Series
6.6.2 Voltage Regulating Circuit VOUT generated from the step-up circuit or VOUT input from the outside produces liquid crystal drive voltage VC via the voltage regulating circuit. The voltage regulating circuit is controlled by liquid crystal drive voltage change command and electronic volume. The S1D15714 Series has a high precision constant voltage source, and incorporates 8-step liquid crystal drive voltage change command and 128-step electronic volume functions. This makes it possible to provide a high precision liquid crystal drive voltage regulation only by the command without adding any external parts. * Electronic volume of Table 6.10 indicates an electronic volume command value. It takes one of 128 states when the data is set in the 7-bit electronic volume register. Table 6.9 shows the value of by setting the data in the electronic volume register.
Table 6.9 D6 0 0 0 1 1 1 D5 0 0 0 1 1 1 D4 0 0 0 1 1 1 D3 0 0 0 1 1 1 D2 0 0 0 1 1 1 D1 0 0 1 0 1 1 D0 0 1 0 1 0 1 0 1 2 125 126 127 V3 Voltage Small
Large
* Liquid crystal drive voltage selection The liquid drive voltage range can be selected from 8 states by the liquid crystal drive voltage select command using the 3-bit crystal drive voltage select command register. Table 6.10 shows V3 voltage output ranges at 25C.
Table 6.10 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 V3 voltage output range 5.6 to 7.0V 6.3 to 7.8V 7.1 to 8.9V 8.0 to 10.0V 9.2 to 11.4V 10.3 to 12.8V 11.7 to 14.5V 12.8 to 16.0V
Rev. 1.0
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S1D15714 Series
*V3 Output Voltage Value Table 6.11 and Fig. 6.6 show logical values of V3 at 25C. Regard the dispersion to logical values as 3%. Table 6.11 Unit [V] LCD voltage selection D2 D1 D0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
16
V3[V] [] ( = 0 to 127) 5.576+0.0109 x 6.256+0.0122 x 7.125+0.0139 x 8.016+0.0156 x 9.161+0.0178 x 10.26+0.0200 x 11.659+0.0227 x 12.825+0.0250 x
14
12
10
V3
8
6
4
2
0 32 64 96 127 Value of electronic volume
Fig. 6.6
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Rev. 1.0
S1D15714 Series
6.6.3 Liquid crystal drive voltage generation circuit Voltages V3 is converted by resistive divider to produce V2, V1, VC, MV1 and MV2 voltages. V2, V1, VC, MV1 and MV2 voltages are impedance-converted by the voltage follower, and is supplied to the liquid crystal drive circuit. A bias ratio is chosen by the bias set command.
Table 6.12 LCD bias set command register contents Bias change command register value (D1, D0) 1/8 bias (0, 0) 1/6, 7 bias (0, 1) 1/5, 3 bias (1, 0) 6/8*V3 16/20*V3 14/16*V3 5/8*V3 13/20*V3 11/16*V3 4/8*V3 10/20*V3 8/16*V3 3/8*V3 7/20*V3 5/16*V3 2/8*V3 4/20*V3 2/16*V3
V2 V1 VC MV1 MV2
Rev. 1.0
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S1D15714 Series
6.6.4 Examples of the peripheral circuits of the power circuit 1 When using all the built-in power supply When using the quintuple-boosting (C: 12 units VDD = VDI = 3.0 V)
VDD VOUT VDD2 CAP1+ CAP1- CAP3+ CAP5+
When using the quadruple-boosting (C: 13 units)
VDD VOUT VDD2 CAP1+ CAP1- CAP3+ CAP5+
+ C1 + C1 C1 +
+ C1 + VDD VSS C1 C1 C1 +
VDD VSS
+ C1
S1D15714 Series
S1D15714 Series
+ C1 C1 +
CAP4+ CAP2- CAP2+
VDD2 VSS C1 VDI VSS + C2 x 6 + + + + + +
CAP4+ CAP2- CAP2+
VDD2 VSS
+ C1 + C1
VDI VSS
+
C2 x 6 + + + + +
V3 V2 V1 VC MV1 MV2 MV3(VSS)
V3 V2 V1 VC MV1 MV2 MV3(VSS)
When using the triple-boosting (C: 12 units)
VDD VOUT VDD2 CAP1+ CAP1- CAP3+ CAP5+
When using the double-boosting (C: 11 units)
VDD VOUT VDD2 CAP1+ CAP1- CAP3+ CAP5+
+ C1 + C1
+ C1 + VDD VSS + C1 C1
VDD VSS
+ C1
S1D15714 Series
S1D15714 Series
C1
+
CAP4+ CAP2- CAP2+
VDD2 VSS
+ C1 + C1 + C2 x 6 + + + + + CAP4+ CAP2- CAP2+
VDD2 VSS
+ C1 + C1
VDI VSS
VDI VSS
+
C2 x 6 + + + + +
V3 V2 V1 VC MV1 MV2 MV3(VSS)
V3 V2 V1 VC MV1 MV2 MV3(VSS)
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Rev. 1.0
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2 V3 adjusting circuit and LCDV circuit VOUT external input (C: 9 units) 3 LCDV circuit only V3 external input (C: 8 units)
C1 VOUT
VDD + VOUT VDD2 CAP1+ CAP1- CAP3+ CAP5+
VDD VOUT VDD2 CAP1+ CAP1- CAP3+ CAP5+
VDD VSS
+ C1
VDD VSS
+ C1
S1D15714 Series
CAP4+ CAP2- CAP2+ C2 x 6 + + + + +
VDD2 VSS
S1D15714 Series
VDI VSS
+ C1
V3 C2 x 6 + + + + +
CAP4+ CAP2- CAP2+
VDD2 VSS
VDI VSS
+ C1
+
V3 V2 V1 VC MV1 MV2 MV3(VSS)
+
V3 V2 V1 VC MV1 MV2 MV3(VSS)
4 External power supply only External input (C: 2 unit)
5 Connection Example of Smoothing Capacitor for Liquid Crystal Drive Voltage In addition to the connections shown in the above 1 to 3, the following connection is also possible.
V3 V2 V1 VC MV1 MV2 MV3(VSS)
VDD VOUT VDD2 CAP1+ CAP1- CAP3+ CAP5+
VDD VSS
+ C1
+ + + + +
S1D15714 Series
CAP4+ CAP2- CAP2+
VDD2 VSS
VDI VSS
+ C1
External Power Supply
V3 V2 V1 VC MV1 MV2 MV3(VSS)
Rev. 1.0
EPSON
S1D15714
C2 x 6 +
23
S1D15714 Series
Examples of common reference settings Item Settings Unit C1 1.0 to 4.7 F C2 0.1 to 1.0 *1 Optimum values of C1 and C2 above vary depending on the LCD panel to be driver. Above values should be referenced as information only. It is recommended to check how patterns with hish-load are displayed before finalizins the values. *2 When the display panel is large and sufficient display dignity is not available by driving the built-in power supply circuit only, do not use the built-in power supply circuit and supply the voltage for driving the LC from outside. 6.6.5 Precautions at Mounting COG When mounting the COG, there are resistance components caused by ITO wiring between the IC or external connecting parts (capacitor, resistor) and the power supply. These resistance components may degrade liquid crystal display dignity or may malfunction the IC. When designing modules, take the following three points into account and evaluate them under the practical prerequisites: (1) Minimize the resistance between the IC pin and the external connecting parts. This IC's boosting circuit is switched with a transistor with very low ON resistance. In mounting the COG, ITO's wiring resistance gets into the switching transistor in series and controls the boosting capacity. Try to make the ITO wiring as thick as possible considering proper wiring to each boosting capacitor. (2) Minimize the resistance to the IC power supply pin. When current flow changes momentarily as in case of display clock switching, the supply voltage may drop momentarily sometimes. When the ITO's wiring resistance to the power supply pin is high, the supply voltage fluctuates greatly inside the IC and may malfunction the IC. Consider proper wiring of the power line so that stable supply voltage can be supplied to the IC. In addition, the power supply VDD2 is provided to this IC separately from the power supply VDD for the logical circuit. When the logical circuit is influenced by noises generated to the power supply circuit if VDD and VDD2 are short-circuited, provide this IC with a power supply independent from VDD and VDD2 or supply a liquid crystal drive voltage from outside without using the built-in power supply. [Current Load Characteristics of Built-in Boosting Circuit (Reference Value)]
100 90
Boosting efficiency [%]
5V x Triple, 0 5V x Triple, 100
80 70 60 50 40 30 0 0.2 0.4 0.6
[Conditions] VDD = VDD2 = 5V, 3V Triple boosting, Quadruple boosting Boosting capacitor 1F Add 50 to both VDD and VSS in series to the power supply.
3V x Quadruple, 0 3V x Quadruple, 100
0.8
1
VOUT pull-out current [mA]
Fig. 6.9 Current load characteristics of built-in boosting circuit without resistance between each CAP pin and capacitor but with /100. This figure shows changes of the boosting efficiency when the current is pulled out from the VOUT pin and when the VOUT voltage is made 100% at the time of OUT=0mA. (3) Prepare a COG module sample by changing the sheet resistance. Evaluate the sample after changing the resistance value of the ITO wiring and select the one with sheet resistance as well as some operation margin.
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Rev. 1.0
S1D15714 Series
6.6.6 Temperature gradient select circuit This is a circuit to select the temperature gradient characteristics of the liquid crystal drive power supply voltage. Temperature gradient characteristics can be selected from eight states by the Temperature Gradient command. Selection of temperature gradient characteristics conforming to the temperature characteristics of the liquid crystal to be used makes it possible to configure a system without providing an external element for temperature characteristics compensation.
6.7 Temperature sensor circuit
The S1D15714 Series incorporate a temperature sensor circuit with an analog voltage output pin of the temperature gradient -4.70 mV/C (Typ.). Input a proper electronic volume resistor value corresponding to the temperature sensor output value from the MPU to control the liquid crystal drive voltage V3, and liquid crystal displays of proper tint will become possible in a wide temperature range. In order to control liquid crystal drive voltage more precisely, construct a system that feeds back values sampled output voltages at a certain temperature to the MPU and saves them as reference voltages to absorb dispersions of output voltages. When a large current load is caused to the IC due to high-speed writing in the display RAM, the internal power supply of the IC will be vibrated and correct values may not be output at certain temperature sometimes. So, read temperature sensor outputs only when a large current load is not caused to the IC. For pins related to the temperature sensor, see 5. Pin Description and 5.5 Temperature Sensor Pin, and for electric characteristics, see 9. DC Characteristics and 9.2 Characteristics of Temperature Sensor.
6.8 Reset circuit
When the RES input becomes LOW, this LSI is set to the initialized state. The following shows the initially set state: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Display : OFF Display : normal mode Display all lighting : OFF Common output status : normal Display start line : Set to 1st line Page address : Set to 0 page Column address : Set to 0 address Display data input direction : Column direction Column address direction : forward n-line a.c. reverse drive : OFF (reverse drive for each frame) n-line reverse drive register : (D3, D2, D1, D0) = (1, 1, 0, 0) DUTY register : (D3, D2, D1, D0) = (0, 0, 1, 1) (1/ 64 duty) Start spot (block) register : (D3, D2, D1, D0) = (0, 0, 0) (COM0) Read modify write : OFF Built-in oscillation circuit : stop Oscillation frequency register : (D3, D2, D1,D0) = (0, 0, 0, 0) (60kHz (TBD)) Power control register : (D2, D1, D0) = (0, 0, 0) LCD drive voltage selection resister : (D2, D1, D0) = (0,0,0) LCD bias change register : (D1, D0) = (0, 0) Electronic volume register : (D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0) 20. Discharge : ON (only for when RES = LOW) 21. Power save : OFF 22. Temperature gradient resistor : (D2, D1, D0) = (0, 0, 0) (-0.06/C) 23. Register data in the serial interface : Clear 24. MLS drive select register: (D4, D3, D2, D1, D0) = (0, 1, 0, 1, 1) (Non-dispersion drive) 25. Temperature sensor When the Reset command is used, only the abovementioned inilialized items 7, 8 and 13 are executed. When power is turned on, initialization by the RES pin is necessary. After initialization by the RES pin, each input pin must be controlled correctly. Furthermore, when control signals from the MPU have a high impedance, the excessive current may flow to the IC. After VDD is applied, measures should be taken to ensure that the input pin does not have a high impedance. The S1D15714 Series discharges the electric charge of VOUT and liquid crystal drive voltage (V3,V2, V1, VC, MV1, MV2) at the level of RES pin = LOW. When liquid crystal drive external power supply is used, external power supply should not be supplied during the period of RES = LOW to prevent external power supply and VDD and VSS from being short circuited.
13. 14. 15. 16. 17. 18. 19.
Rev. 1.0
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S1D15714 Series
7. COMMAND
The S1D15714 Series identifies data bus signals by a combination of A0, RD(E) and WR(R/W). Interpretation and execution of the command are executed by the internal timing alone which is independent of the external clock. This allows high-speed processing. The 80 series MPU interface allows the command to be started by entering the low pulse in the RD pin during reading and by entering the low pulse in the WR pin during writing. The 68 series MPU interface allows a read state to occur by entering HIGH in the R/W pin, and permits a write state to occur by entering LOW. It also allows the command to be started by entering the high pulse in the pin E. (For timing, see the description of "10. Timing characteristics"). Accordingly, the 68 series MPU interface is different from 80 series MPU interface in that RD(E) is "1(H)" in the case of display data/read shown in the Command Description and Command Table. The following describes the commands, based on the example of the 80 series MPU interface: When the serial interface is selected, enter data sequentially starting from D7.
Command Description
(1) Display ON/OFF This command sets the display ON/OFF. When Display OFF is specified, the driver common to segments outputs the VC level. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 Output level Display OFF Display ON
(2) Display Normal/Reverse This command allows the display ON/OFF state to be reversed, without having to rewrite the contents of the display data RAM. In this case, contents of the display data RAM are maintained. E RD 1 R/W WR 0
A0 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 1
D1 1
D0 0
1
Setting RAM data = HIGH LCD ON Voltage (normal) RAM data = LOW LCD ON Voltage (reverse)
(3) Display All Lighting ON/OFF This command forces all the displays to be turned on independently of the contents of the display data RAM. In this case, the contents of the display data RAM are maintained. Fully white display can also be made by a combination of the Display Reverse command. E RD 1 R/W WR 0
A0 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 1
D1 0
D0 0 1
Setting Normal display status Display all lighting
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(4) Common Output Status Select This command allows the scanning direction of the COM output pin to be selected. For details, see the description of "6.5.2 COM Drivers" in the Function Description. A0 0 E RD 1 R/W WR D7 D6 D5 D4 D3 D2 D1 D0 0 11000100 Normal 1 Reverse Selected state COM0 COM63 COM63 COM0
COMS COMS
(5) Display Start Line set (2-byte command) The parameter following this command specifies the display start line address of the display data RAM shown in Fig. 6.4. The display area is indicated in the direction where line address numbers are incremented, starting from the specified line address. If a dynamic change of the line address is made by this command, smooth scrolling in the longitudinal direction and page breaking are enabled. For details, see the description of "6.2.3 Line address circuit" in the Function Description. A0 0 1 E RD 1 1 R/W WR 0 0 D7 1 L7 D6 0 L6 D5 0 L5 D4 0 L4 D3 1 L3 D2 0 L2 D1 1 L1 D0 0 L0
Mode setting Register setting
* Display Start Line Set command parameter L7 * * * L6 * * * L5 0 0 0 L4 0 0 0 * * 1 1 1 1 1 * * 1 1 1 1 1 Set to line address 000H at the time of resetting. * : denote invalid bits. 0 1 L3 0 0 0 L2 0 0 0 L1 0 0 1 L0 0 1 0 Line address 00H 01H 02H 3EH 3FH
* Line address setting sequence
Set Line Address Mode Set Line Address Register No Reset Line Address Mode Change Completed? Yes
Fig. 7.1
Rev. 1.0
EPSON
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S1D15714 Series
(6) Page Address Set This command specifies the page address corresponding to row address when MPU access to the display data RAM shown in Fig. 6.4. The column address is split into two sections (higher 4 bits and lower 4 bits) when it is set. Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read and write the display data. For details, see the description of "6.2.2 Page address circuit" in the Function Description. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 1 D3 P3 D2 P2 D1 P1 D0 P0 Page address Page address set *: denote invalid bits. P3 0 0 0 1 P2 0 0 1 0 1 0 1 0 P1 0 0 P0 0 1 Page address Page 0 Page 1 Page 7 Page 8
(7) Column Address Set This command specifies the column address of the display data RAM shown in Fig. 6.4. A column address should be set separately, higher 4 bits and lower 4 bits. Since the increment (+1) of the column address is carried out automatically everytime a display data RAM is accessed MPU can Read/Write display data continuously. Please refer to 6.2.2 column address circuits of functional explanation for more details. A0 0 0 E RD 1 1 R/W WR 0 0 D7 0 0 D6 0 0 D5 0 0 D4 1 0 D3 C7 C3 D2 C6 C2 D1 C5 C1 D0 C4 C0
Column address higher set Column address lower set Column address 00H 01H 02H A6H A7H
C7 0 0 0 1 1
C6 0 0 0 0 0
C5 0 0 0 1 1
C4 0 0 0 0 0
C3 0 0 0 0 0
C2 0 0 0 1 1
C1 0 0 1 1 1
C0 0 1 0 0 1
(8) Display Data Write This command allows the 8-bit data to be written to the address specified by the display data RAM. After writing, column address or page address is automatically incremented +1 by the Display Data Input Direction Select command. This enables the MPU to write the display data continuously. E RD 1 R/W WR 0
A0 1
D7
D6
D5
D4 D3 Write Data
D2
D1
D0
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(9) Display Data Read This command allows the 8-bit data to be read from the address specified by the display data RAM. After reading, column address or page address is automatically incremented +1 by the Display Data Input Direction select command. This enables the MPU to read multiple word data continuously. It should be noted that one dummy reading is essential immediately after the column address or page address has been set. For details, see the description of "6.1.5 Access to display data RAM and internal register" in the Function Description. When the serial interface is used, display data cannot be read. E RD 0 R/W WR 1
A0 1
D7
D6
D5
D4 D3 Read Data
D2
D1
D0
(10) Display Data Input Direction Select This command sets the direction where the display RAM address number is automatically incremented. For details, see the description of "6.2.3 Column address circuit" in the Function Description. E RD 1 R/W WR 0
A0 0
D7 1
D6 0
D5 0
D4 0
D3 0
D2 1
D1 0
D0 0 1
Direction Column Page
(11) Column Address Set Direction This command can reverse the relationship between the display RAM data column address and segment driver output shown in Fig. 6.4. So you can reverse the sequence of segment driver output pins using this command. When the display data is written or read, the column address is incremented by (+1) according to the column address given in Fig. 6.4. For details, see the description of "6.2.2 Column address circuit" in the Function Description. E RD 1 R/W WR 0
A0 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 0
D1 0
D0 0 1
Setting Normal Reverse
(12) n-line Inversion Drive Register Set This command sets the liquid crystal alternating drive reverse line count in the register to start line reverse driving operation. The line count to be set is 4 to 60 (15 states for each 4 lines. For details, see the description of "6.4 Display timing generation circuit" in the Function Description. E RD 1 R/W WR 0
A0 0
D7 0
D6 0
D5 1
D4 1
D3 N3
D2 N2
D1 N1
D0 N0
Reverse line count Reverse line count
N3 0 0 1 1
N2 0 0 1 1
N1 0 0 0 1
N0 0 1 1 0
Reverse line count 4 (1 x 4) 8 (2 x 4) 56 (14 x 4) 60 (15 x 4)
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(13) n-line Inversion Drive ON/OFF This command provides ON/OFF control of n-line inverting drive. E RD 1 R/W WR 0
A0 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 1
D1 0
D0 0 1
n-line OFF ON
(14) Duty Set Command Liquid crystal drive at a lower power consumption is ensured by using this command to change the duty. Use of this command also allows display at a desired position on the panel (continuous CON pins + COM on a 4-line basis). This command is used with a pair of the duty set parameter and start point (block) parameter, so be sure to set both parameters so that one of them will immediately follow the other. A0 0 0 E RD 1 1 R/W WR 0 0 D7 0 U3 D6 1 U2 D5 1 U1 D4 0 U0 D3 1 S3 D2 1 S2 D1 0 S1 D0 1 S0 Selected state Duty set command Duty set, Start point set *: denote invalid bits. * Duty set Duty can be set in the range from 1/5 duty to 1/65 duty by 4 steps. It should be set in higher 4 bits (D7, D6, D5, D4). Set to 1/65 duty after resetting. U3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 U2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 U1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 U0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display duty 1/5 1/9 1/13 1/17 1/21 1/25 1/29 1/33 1/37 1/41 1/45 1/49 1/53 1/57 1/61 1/65
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* Start point (block) register set parameter Use this parameter to set 4-bit data in the start point (block) register. Then one of 16 start point blocks will be determined. It should be set in lower 4 bits (D3, D2, D1, D0). S3 0 0 0 1 1 S2 0 0 0 1 1 S1 0 0 1 1 1 S0 0 1 0 0 1 Start piont setting 0 (COM0 to 3) 1 (COM4 to 7) 2 (COM8 to 11) 14 (COM56 to 59) 15 (COM60 to 63)
Set to 0 block at the time of resetting *1 Voltage optimum to liquid crystal drive is changed when the duty is changed. Use the electronic volume and set the voltage to get the optimum display. *2 For display scroll, use (5) Display Start Line Set Command, and do not scroll displays by using this command. * Duty command setup example 1. Duty 1/49 When 1 (COM4 to COM7) is specified as the start point (block) Display area COM4 to COM51, COMS 2. Duty 1/33 When 10 (COM44 to COM47) is specified as the start point (block) Display area COM44 to COM63 and COM0 to COM11, COMS * When the COM pin is not commonly used for the master and the slave in a master/slave two-chip operation (SEG 168 pieces are made common and two screens of 168x120dots are driven up and down with COM 60 pieces + COM 60 pieces), the display thick will become different between the master-side display area and the slave-slave display area unless the master and the salve a re of the same duty. Set a same duty to both the master and the slave. When either the master side or the slave side is not displayed, input the Display OFF Command to the side, which you do not want to display, so that the VC level is output. (15) Read Modify Write This command is paired with end command for use. If this command is entered, the column address is not changed by the Display Data Read command. It can be incremented +1 by the Display Data Read command alone. This state s retained until the End command is input. If the End command is input, the column address goes back to the address when the Read Modify Write command is input. This function reduces the MPU loads when changing the data repeated in the specific display area such as blinking cursor. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
* A command other than display data Read/Write command can be used in the Read Modify Write mode. However, you cannot use the column address set command.
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* Sequence for cursor display
Page Address Set Column Address Set
Read Modify Write
Dummy Read Data Read Data Manipulation Data Write No Change Completed? Yes End
Fig. 7.2
(16) End This command releases the read modify write mode and gets column address back to the initial address of the mode. E RD 1 R/W WR 0
A0 0
D7 1
D6 1
D5 1
D4 0
D3 1
D2 1
D1 1
D0 0
Return
Column address
N
N+1
N+2
N+3
***
N+m
N End
Set read-modify-write mode
Fig. 7.3
(17) Built-in Oscillator Circuit ON/OFF This command starts the built-in oscillator circuit operation. It is enabled only in the master operation mode (M/S = HIGH) when built-in oscillator circuit is valid (CLS = HIGH). When the built-in power supply is used, the Oscillator Circuit ON command must be executed before the Power Control Set command. (See the description of "(21) power control command"). If the built-in oscillator circuit is turned off when the built-in power supply is used, display failure may occur. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0 1 Built-in oscillator circuit OFF ON
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(18) Built-in Oscillator Circuit Frequency Select This command sets the built-in oscillator circuit frequency. The frequency can be selected whether the built-in oscillator circuit is turned on or off. A0 0 E RD 1 R/W WR 0 D7 0 D6 1 D5 1 D4 1 D3 F3 D2 F2 D1 F1 D0 F0 fCL kHz Frequency Set
F3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
F2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
F1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
F0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CL Frequency fCL [kHz] 100 86.8 78.0 69.8 65.1 59.4 55.3 51.3 49.0 45.8 43.5 41.0 39.4 37.4 35.8 34.1
Frame frequency, fFR [Hz] 1/65Duty 1/49Duty 1/33Duty 92 120 174 80 104 151 72 94 135 64 84 121 60 78 113 55 71 103 51 66 96 47 62 89 45 59 85 42 55 80 40 52 75 38 49 71 36 47 68 34 45 65 33 43 62 31 41 59
(F3, F2, F1, F0) = (0, 0, 0, 0) is set after resetting. * The values in the above table are representative values at 25C. Consider that there are dispersions of 8% at 25C. fFR means the cycle to rewrite a screen (frame frequency) and is calculated from the following equation:
fFR =
(n + 3) x 16
fCL
(n = 1/Duty)
This does not indicate the frequency of the fFR signal.
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(19) Power Control Set This command sets the built-in power supply circuit function. For details, see the description of "6.6 Power supply circuit" in the Function Description. A0 0 1 E RD 1 1 R/W WR 0 0 D7 0 0 D6 0 0 D5 1 0 D4 0 0 D3 0 0 D2 1 P2 P2 0 1 D1 0 P1 P1 D0 1 P0 P0 Selected state Command Register set
Selected state Step-up: OFF Step-up: ON 0 V3: OFF 1 V3: ON 0 LCD voltage: OFF 1 LCD voltage: ON V3 : Voltage adjustment circuit (V3 adjustment circuit) LCDV : Liquid crystal rive potential (V2, V1, VC, NV1, NV2) generation circuit
An internal clock is required to operate the built-in power supply circuit. During the operation of the built-in power supply circuit, be sure that the internal clock is present inside. If the built-in oscillator circuit is used, execute the built-in oscillator circuit ON command before the power control set command. If an external oscillator circuit is used, operate the external oscillator circuit before the power control set command. If the internal clock is cut off during the operation of the built-in power supply circuit, display failure may occur. To avoid this, do not cut it off.
Built-in oscillator ON
External oscillator input
Power Control Set
A built-in oscillator used
An external oscillator used
Fig. 7.4
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(20) Liquid Crystal Drive Voltage Select The liquid crystal drive voltage range issued from the liquid crystal drive voltage regulating circuit is selected from 3 states by this command. E RD 1 R/W WR 0 V3 voltage output range V3 voltage range set
A0 0
D7 0
D6 0
D5 1
D4 0
D3 0
D2 V2
D1 V1
D0 V0
V2 0 0 0 0 1 1 1 1
V3 voltage V1 V0 output range 0 0 5.6 to 7.0V 0 1 6.3 to 7.8V 1 0 7.1 to 8.9V 1 1 8.0 to 10.0V 0 0 9.2 to 11.4V 0 1 10.3 to 12.8V 1 0 11.7 to 14.5V 1 1 12.8 to 16.0V (V2, V1, V0) = (0, 0, 0) is set after resetting.
(21) LCD Bias Change With this command, the bias ratio of liquid crystal drive voltage should be chosen from 4 states. A0 0 E RD 1 R/W WR 0 D7 0 D6 1 D5 0 D4 1 D3 0 D2 0 D1 B1 D0 B0 Bias ratio Bias ratio set
B1 0 0 1
B0 0 1 0
Bias ratio 1/8 1/6.7 1/5.3
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(22) Electronic Volume This command controls liquid crystal drive voltage V3 issued from the built-in liquid crystal power supply voltage regulating circuit, and adjusts the liquid crystal display density. For details, see the description of "6.6.2 Voltage Regulating Circuit" in the Function Description. A0 0 0 E RD 1 1 R/W WR 0 0 D7 1 R7 D6 0 R6 D5 0 R5 D4 0 R4 D3 0 R3 D2 0 R2 D1 0 R1 D0 1 R0
Mode set Register
* Electronic Volume Mode Set Inputting this command makes the Electronic Volume Register Set Command valid. Once the Electronic Volume Mode Set Command is input, any command other than the Electronic Volume Register Set Command cannot be used. After data are saved in the register by the Electronic Volume Register Set Command, this command is released. * Electronic Volume Register Set When a 7-bit data to the electronic volume register is set by this command, liquid crystal drive voltage V3 assumes one state out of voltage values in 128 states. After this command is input, and the electronic volume register is set, the electronic volume mode is reset. R7 * * * * * R6 0 0 0 1 1 R5 0 0 0 1 1 R4 0 0 0 1 1 1 1 1 1 1 1 0 1 R3 0 0 0 R2 0 0 0 R1 0 0 1 R0 0 1 0 VC Smaller
Larger *: denote invalid bits.
* Electronic volume register set sequence
Set Electronic Volume Mode Set Electronic Volume Register No Reset Electronic Volume Mode Change Completed? Yes
Fig. 7.5
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(23) Discharge ON/OFF This command discharges the capacitors connected to the power supply circuit. This command is used when the system power of this IC (S1D15714 Series) is turned off, and the duty is changed. See the description of (3) Power Supply OFF and (4) Changing the Duty in the Instruction Setup: Reference. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0 1 Setting Discharge OFF Discharge ON
* If this command is executed when the external power supply is used, a large current may flow to damage the IC. If external power supply is used to drive liquid crystal, be sure to turn off the external power supply before executing this command. (24) Power Saving This command establishes the power save mode, thereby ensuring a substantial reduction of current consumption. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 1 Power save mode OFF ON
In the power save mode, display data and operation before power saving are maintained. Access to the display data RAM from the MPU is also possible. The current consumption is reduced to the value close to static current if all operations of the LCD display system are stopped and there is no access from the MPU. In the power save mode, the following occurs: Stop of oscillator circuit Stop of LCD power supply circuit Stop of all liquid crystal drive circuit (VSS level output is issued as the segment and common driver output). When the temperature sensor is set to ON, the sensor circuit operates even under the power saving status. To reduce current consumption, use the Temperature Sensor ON/OFF Command to control current as the need arises. When the Power Save OFF Command is input, the power saving status will be released, and the system will return to the status before the power save mode started. * Power Save Sequence
Optional status Power Save ON Power saving status Power Save OFF Power saving status is released. Return to the status before power saving
Fig. 7.6 * When the external power supply is used, it is recommended to stop the external power supply circuit function when the power save mode is started. For example, when each level of the liquid crystal drive voltage is given from the external resistive divider circuit, it is recommended to add a circuit to cut off the current flowing to the resistive divider circuit when power save function is started. The S1D15714 Series has a liquid crystal display blanking control control pin DOF, and the level goes LOW when power save function is started. You can use the DOF output to stop the external power supply circuit function. Rev. 1.0
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(25) Temperature Gradient Set The 3-bit data of this command is used to set the temperature gradient characteristics of the liquid crystal drive voltage output from the built-in power supply circuit from eight states to one state. The temperature gradient of the liquid crystal drive voltage can be set according to the liquid crystal temperature gradient to be used. This eliminates the need of a temperature characteristics regulating circuit to be installed outside this IC (S1D15714 Series). E RD 1 R/W WR 0 Temperature gradient [%/C] Temperature gradient set
A0 0
D7 0
D6 1
D5 0
D4 0
D3 1
D2 T2
D1 T1
D0 T0
Temperature T2 T1 T0 gradient [%/C] 0 0 0 -0.06 0 0 1 -0.08 0 1 0 -0.10 0 1 1 -0.11 1 0 0 -0.13 1 0 1 -0.15 1 1 0 -0.17 1 1 1 -0.18 (T2, T1, T0) = (0, 0, 0) is set after resetting. *: denote invalid bits.
(26) Status Read This command reads out the temperature gradient select bit set on the register. After inputting the Status Read Mode Set Command, continue reading. After the status reading ends, the Status Read Mode will be released. A0 0 0 E RD 1 0 R/W WR 0 1 D7 1 * D6 0 * D5 0 * D4 0 * D3 1 * D2 1 T2 D1 1 T1 D0 0 T0 Temperature gradient [%/C] Mode Set Register *: denote invalid bits. Temperature gradient [%/C] -0.06 -0.08 -0.10 -0.11 -0.13 -0.15 -0.17 -0.18
T2 0 0 0 0 1 1 1 1
T1 0 0 1 1 0 0 1 1
T0 0 1 0 1 0 1 0 1
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(27) Reset This command resets the column address and the page address to 0 and releases the read modify write mode and test mode without giving adverse effect to the display data RAM. For details, see the description of "6.7 Reset" in Function Description. Resetting is carried out after the reset command has been input. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
Initialization upon application of power supply is carried out by the reset signal to the RES pin. The reset command cannot be used for this purpose. (28) Temperature Sensor ON/OFF ON/OFF of a temperature sensor is specified with this command. A0 0 E RD 1 R/W WR 0 D7 0 D6 1 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 1 Set up Temperature sensor OFF Temperature sensor ON
The temperature sensor off is set up after reset. When using a built-in temperature sensor, the temperature sensor should be ON by using this command. Although there is no problem setting a temperature sensor ON even if it is not used, 10 A grade current is consumed. The temperature sensor circuit is independently controlled from the Power Save Command. (29) MLS Drive Select (2-byte Command) This command is for selecting MLS drives and switches the dispersion drive and the non-dispersion drive. This command is a 2-byte command and is used together with the MLS Drive Select Mode Set Command and the MLS Drive Select Pattern Set Command. Be sure to input the both command in succession. A0 0 0 E RD 1 1 R/W WR 0 0 D7 1 * D6 1 * D5 1 * D4 0 0 D3 0 M3 D2 1 0 D1 1 1 D0 1 1
Mode Set Pattern Set * denotes invalid bit.
M3 0 1
M2 0 0
M1 M0 Pattern Set 1 1 Dispersion Drive 1 1 Non-dispersion Drive The non-dispersion drive is set after resetting.
* The dispersion drive and the non-dispersion drive are liquid crystal driving methods unique to the MLS drive. The SID15714 Series adopt 4-line MLS drive. Selected voltages are output for the period (the period of 4/(65+3) of one frame for 65-line display) of about quadruple the selection period for the normal drive mode in which one line is selected and scanned each time (the period o 1/65 of one frame for 65-line display). In the non-dispersion drive, selection signals of 4-line data are output 4 times in succession. We recommend this drive when displays are frequently changed. In case of the dispersion drive, selection signals are divided into and output 4 times in one frame period. This driving method allows reducing the frame frequency. To reduce consumption current, we recommend this drive. In this case, however, displays may blink, and this drive is not suitable for movie display.
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(30) NOP This is a Non-Operation command. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1
Note: S1D15714 Series maintains the operation status due to the command. However, when exposed to excessive external noise, internal status may be changed. This makes it necessary to take some measures which reduces noise generation in terms of installation or system configuration, or which protects the system against adverse effect of noise. To cope with sudden noise, it is recommended to refresh the operation status on a periodic basis.
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Table 7.1 Table of commands in S1D15714 Series series
Command code A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 01 0101110 1 (2) Display Normal 0 1 01 0100110 /Reverse 1 (3) Display All Lighting 0 1 01 0100100 ON/OFF 1 (4) Common Output 0 1 01 1000100 Status Select 1 (5) Display Start Line Set 0 1 01 0001010 0 1 0* * Display start line address (6) Page Address Set 0 1 01 0110001 * * Page address (7) Column Address Set 0 1 00 0 0 1 Higher column Higher bits address Column Address Set 0 1 00 0 0 0 Lower column Lower bits address (8) Display Data Write 1 1 0 Writes data (9) Display Data Read 1 0 1 Reads data (10) Display Data Input 0 1 01 0000100 Direction Select 1 (11) Column Address Set 0 1 01 0100000 Direction 1 (1) (12) n-line inversion Drive Register Set (13) n-line ON/OFF 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 * 1 1 1 0 0 0 1 1 * 1 1 0 1 * 1 0 1 * 1 0 1 1 * 1 1 0 1 0 0 0 0 Command Display ON/OFF Function LCD display ON/OFF control. 0: OFF, 1: ON LCD display normal/reverse 0: Normal, 1: Reverse Display All Lighting 0: Normal display, 1: All ON Selects COM output scan direction. 0: Normal, 1: Reverse Sets display start line. Sets the display RAM page address.
(14) Duty Set Command 0 Duty Set Static spot set 0 (15) Read Modify Write 0 (16) End (17) Built-in Oscillator Circuit ON/OFF (18) Built-in Oscillator Circuit Frequency Select (19) Power Control Set (20) Liquid Crystal Drive Voltage Select (21) LCD bias change (22) Electronic Volume Mode Set Electronic Volume Register Set (23) Discharge ON/OFF (24) Power Save ON/OFF (25) Temperature Gradient Select (26) Stator Read (27) Reset (28) Temperature Sensor ON/OFF (29) MLS Drive Select (2-byte command) (30) NOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Higher 4 bits of column address in Display RAM are set. Lower 4 bits of column address in Display RAM are set. Writes data to the display RAM. Reads data to the display RAM. Display RAM data input direction 0: Column direction 1: Page direction Compatible with display RAM address SEG output 0: Normal 1: Reverse 1 1 Invert line count Line invert drive. Sets the line count. 100100 Resets the line invert drive. 0: n-line OFF 1: n-line ON 101101 2 byte command Static spot (block) 100000 Increments the column address. Increments +1 in the write mode. Does not increment in the read mode. 101110 Resets read modify write functions. 101010 Built-in oscillator circuit operation 1 0: OFF, 1: ON 1 1 Frequency 1 1 1 0 0 0 0 0 1 Operation state Selects built-in power supply operation state. 0 V3 range 0 0 0 0
bias
0 1
Bias ratio select V3 output voltage is set to the electronic volume register. 128 states Discharges Power supply circuit connection capacitor. 0: OFF (normal), 1: ON Power Save 0: OFF, 1: ON
Electronic volume 1 0 1 0 * 1 1 1 * 1 1 1 0 0 * 1 1 1 * 1 0 0 0 0 * 0 0 0 0 0 1 1 0 0 1 0 0 1
0 1 1 Temperature gradient Sets to 8 steps. 1110 *Temperature gradient 0010 1 0 MLS 0 0 1 0 0 0 1 1 1 0 1 1 1
Issues the temperature gradient select bit. * : denote invalid bits. Resets the column, page and address registers.Resets the read modify write function. Temperature sensor 0 : OFF (normal), 1 : ON Mode Set MLS 0 : Dispersion, 1: Non-dispersion Non-operation command
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S1D15714 Series Instruction Setup Example (Reference)
(1) Initial setup
VDD - VSS, VDD2 - VSS power turns on when RES terminal = LOW.
Stable power supply
Release the reset state. (RES terminal = HIGH) *1
Function setup by command entry (set by users) (11) Column address set direction (4) Common output status select (2) Display normal/reverse (3) Display all lighting ON/OFF (14) Set the duty (20) LCD voltage select (22) Electronic volume (25) Temperature gradient set (When the n-line AC invert drive is used) Function setup by command entry (set by users) (12) n-line invert drive register set (13) n-line ON/OFF (When the built-in CR oscillator circuit is used) Function setup by command entry (set by users) (18) Built-in oscillator circuit frequency select (17) Built-in oscillator circuit ON/OFF (When the built-in LCD power supply circuit is used) Function setup by command entry (set by users) (21) LCD bias change (19) Power control set (When the external oscillator circuit is used) Enter the external clock (When the n-line invert drive is not used)
(When the external LCD power supply circuit is used) External LCD power supply entry
Initialization completed
Note: *1 DDRAM contents are not determined even in the initialized state after resetting. See "6.7 Reset Circuit" in the "6. Function Description". * Numerals in the command parenthesis correspond to the numerals of the items in Command Description.
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(2) Data display
End of initialization
Function setup by command entry (set by users) (5) Display start line set (10) Display data input direction select (6) Page address set (7) Column address set
Function setup by command entry (set by users) (8) Display data write
Function setup by command entry (set by users) (1) Display ON/OFF command
End of data display
Note:
* DDRAM contents are not determined after end of initialization. Write data to all the DDRAM used for display. See "9. Display data write" in the "7. Command Description".
(3) Power OFF
A desired state
Function setup by command entry (set by users) (24) Power save ON (When an external LCD power supply circuit is used) External LCD power supply OFF (When the built-in power supply circuit is used) Function setup by command entry (set by users) (28) Discharge ON
Reset state (RES terminal = LOW)
Set the time (tL) from the beginning of the reset status to VDD, VDD2VSS power supply OFF longer than the time (tH) required when the liquid crystal drive potentials (MV2, MV1, VC, V1, V2, V3) fall below the liquid crystal threshold voltage (about 1V as the guide).
VDD2 - VSS, VDD - VSS power supply OFF
Note:
* This IC controls the circuit of the liquid crystal drive power supply system using the VDD, VDD2-VSS power supply circuit. If the VDD, VDD2-VSS power supply is cut off with voltage remaining in the liquid crystal drive power supply system, voltage not controlled will be issued from the SEG and COM pins, and this may result in display failure. To avoid this, follow the above-mentioned power off sequence.
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(4) How to change the duty
A desired state
Function setup by command entry (set by users) (1) Display OFF
Function setup by command entry (set by users) (24) Power save ON
Function setup by command entry (set by users) (23) Discharge ON
Function setup by command entry (set by users) (22) Electronic volume (18) Built-in oscillator circuit frequency select (14) Duty set When the n-line reversing command is used : (12) n-line reverse drive register set Secure an interval of 30ms or more between "discharge ON" to "discharge OFF".
Function setup by command entry (set by users) (23) Discharge OFF
Function setup by command entry (set by users) (24) Power save OFF
End of duty change
Note:
* In the above sequence, the display disappears for the time from Power Save ON to Power Save OFF + about 350ms (in case of frame frequency 80Hz). When the Duty Set Command is executed while the liquid crystal display is on, there may occur the trouble that the display blinks momentarily. Observe the above sequence strictly.
(5) Refresh It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise.
A desired state
Set all commands to the ready state (Including default state setting.)
Refreshing of DRAM
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8. ABSOLUTE MAXIMUM RATINGS
Table 8.1 Item Power voltage (1) Power voltage (2) Power voltage (3) when external input Power voltage (4) Power voltage (5) Input voltage Output voltage Operating temperature Storage temperature Symbol VDD VDD2 VDI V3, VOUT V2, V1, VC, MV1, MV2 VIN VO TOPR TSTR VSS = 0V unless otherwise specified. Specified value -0.3 to +6.0 -0.3 to +6.0 -0.3 to 3.6 -0.3 to 18.0 -0.3 to V3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -40 to +85 -55 to +125 Unit V
C
bare chip
VOUT V3
VDD2 V2, V1, VC, MV1, MV2 VCC VDD (VDI) GND System (MPU) side VSS S1D15714 side
Fig. 8.1 Notes: 1. VoltagesV3, V2, V1, VC, MV1, MV2 and MV3 (VSS) must always meet the conditions of V3V2V1VCMV1MV2MV3 (VSS). 2. Voltage VOUT must always meet the conditions of VOUTVDD2VDD. When inputting VOUT from outside, maintain the condition of VOUT V3+0.2V. 3. If the LSI has been used in excess of the absolute maximum rating, it may be subjected to permanent breakdown. So in the normal operation, the LSI is preferred to be used under the condition of electrical characteristics. If this condition is not met, LSI operation error may occur and LSI reliability may be deteriorated.
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9. DC CHARACTERISTICS
VSS = 0V, VDD = (5V10%) and Ta = -40 to +85C unless otherwise specified. Table 9.1
Item Working voltage (1) Operation enabled Symbol VDD Conditions -- -- External input -- -- VDD=2.7V to 5.5V Specified value Min. Typ. Max. 2.7 VDD 2.7 VDD2 5.6 0.8xVDD VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 5 0.3 5 8 100 100 5.5 5.5 3.3 16.2 16.2 VDD 0.2xVDD VDD 0.2xVDD VDD 0.2xVDD VDI 0.2xVDI 1 3 20 10 5 20 16 108 108 A k A pF kHz kHz Unit V Applicable pin VDD *1 VDD2 VDI VOUT V3 *2 *3 *3 *4 *4 *5 *5 *6 *6 *7 *8 SEGn COMn *9 VDD *10 V3 -- *11 *11
Working voltage (2) Operation enabled VDD2 Working voltage (3) Operation enabled VDI
Working voltage (4) Operation recommended VOUT Working voltage (5) Operation enabled High-level input voltage Low-level input voltage High-level output voltage (1) Low-level output voltage (1) High-level output voltage (2) Low-level output voltage (2) High-level output voltage (3) Low-level output voltage (3) Input leak current Output leak current LCD driver ON resistance Static current consumption Input pin capacity Oscillation frequency Internal oscillation External input V3 VIHC VILC
VOHC1 VDD=2.7V VOLC1 to 5.5V VOHC2 VDD=2.7V VOLC2 to 5.5V VOHC3 VDD=2.7V VOLC3 to 3.3V ILI ILO RON IDDQ I3Q CIN fCL fCL
IOH=-25A 0.8xVDD IOL=25A VSS IOH=-100A 0.8xVDD IOL=100A VSS IOH=-100A IOL=100A 0.8xVDI VSS -1 -3 -- -- -- -- -- 92 92
VIN=VDD or VSS Ta=25C V3=7.2V V3=14.0V Ta=25C VDD=3.0V V3=16V Ta=25C, f=1MHz Ta=25C at the maximum frequency Ta=25C at the maximum frequency
[Asterisked references] *1. Does not guarantee if there is an abrupt voltage variation during MPU access. *2. For VDD2 and V3 system operating voltage range, see Fig. 9.4. Applicable when the external power supply is used. *3. A0, D0 to D5, D6(SCL), D7(SI), RD(E), WR(R/W), CS, CS2, CLS, CL, FR, F1, F2, SYNC, M/S, C86, P/S, DOF, RES, TEST and TEST 1 pins. *4. Do to D7 pin. *5. CL pin. *6. FR, DOF, F1, F2, SYNC pins. *7. A0, RD(E), WR(R/W), CS, CLS, M/S, C86, P/S, RES, TEST and TEST 1 pins. *8. Applicable when D0 to D5, D6(SCL), D7(S1), CL, FR, DOF, F1, F2 and SYNC pins have a high impedance. *9. Indicates the resistance when 0.1V voltage is applied between the output pin SEGn or COMn and each power supply (V2, V1, VC, MV1, MV2). RON =0.1V/I (where I denotes current when 0.1V is applied when power is on). *10. Current value when TEST1 = LOW *11. For the relations between oscillation frequency and frame frequency, see Table 9.7. Specified values of external input items are recommended.
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Table 9.2
Item Input voltage Symbol VDD2 VDD2 VDD2 VDD2 VDD2 VOUT V3 Conditions Equal boosting Double boosting Triple boosting Quadruple boosting Quintraple boosting -- -- Specified value Min. Typ. Max. 2.7 2.7 2.7 2.7 2.7 -- 5.6 -- -- -- -- -- -- -- 5.5 5.5 5.3 4.0 3.2 16.2 16.2 Unit V Applicable pin VDD2
Built-in power circuit
Amplified output voltage Voltage adjusting circuit operating voltage
VOUT V3 *12
*12.
The V3 voltage adjusting circuit is adjusted within the electronic volume operating range.
Dynamic current consumption value (1)
The built-in power supply is ON while the display is on. Table 9.3 All displays in white
1/65 Duty VDD 5V Boosting Triple V3 voltage 14V 10V Double 3V Quintuple Quadruple Triple 8V 14V 10V 8V Typ. 64 61 60 74 61 57 Min. 107 102 100 123 102 95 1/33 Duty Typ. 48 45 42 -- 47 42 Min. 80 75 70 -- 78 70 Unit A Remarks *13
Symbol : ISS(1)
[* marked section: Refer to page 51.]
Table 9.4 Display heavy load display *14 Symbol : ISS(1)
1/65 Duty VDD 5V Boosting Triple V3 voltage 14V 10V Double 3V Quintuple Quintuple Triple 8V 14V 14V 8V Typ. 103 82 72 128 86 72 Min. 172 137 120 213 143 120 1/33 Duty Typ. 66 55 47 -- 58 49 Min. 110 92 78 -- 97 82 Unit A Remark *13
[* marked section: Refer to page 51.]
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S1D15714 Series
* Current consumption under power saving mode: VSS = 0V, VDD = 5V, TEST1 = HIGH, Ta = 25C Table 9.5 Item Sleep state Symbol IDDS1 Condition -- Specified value Min. Typ. Max. -- 6 20 Unit A Remarks --
* Current Consumption at power saving(2) VSS = 0V, VDD = VDI = 3V, TEST1 = LOW, Ta = 25C Table 9.6 Temperature sensor characteristics Item Sleep state Symbol IDDS1 Condition -- Specified value Min. Typ. Max. -- 0.3 5 Unit A Applicable pin --
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[Reference Data 1] * Dynamic current consumption during LCD display when the internal power supply is used. V3 = 14V *13
150
100
ISS (1) [A]
VDD = VDD2 = 5V, Triple boosting Display heavy load pattern
VDD = VDD2 = 5V, Triple boosting All displays in white 50
0
33 1/Duty
65
Fig. 9.1
[Reference Data 2] * Dynamic current consumption during LCD display when the internal power supply is used. V3 = 10V *13
100
VDD = VDD2 = 3V, Quadruple boosting Display heavy load pattern VDD = VDD2 = 5V, Triple boosting Display heavy load pattern
ISS (1) [A]
VDD = VDD2 = 3V, Quadruple boosting All displays in white 50 VDD = VDD2 = 5V, Triple boosting All displays in white
0
33 1/Duty
65
Fig. 9.2 [For the items marked with *, see Page 51.]
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S1D15714 Series
[Reference Data 3] * Dynamic current consumption during access
10 This indicates the current consumption when the heavy load pattern is always written by fcyc. When not accessed, only ISS(1) remains. 1
[mA]
ISS (3)
Conditions : VDD = VDD2 = 5.0V, V3 = 14V *13
0.1
0.01 0.001 0.01 fCYC 0.1 [MHz] 1 10
Fig. 9.3
[Reference Data 4] * Operating voltage range of VDD and V3 Systems (Applicable when an external power supply is used.)
20
16.2 15
[V]
10
V3
Operation Voltage range
5.6 5
0 0
2.7 2 VDD2 4 [V]
5.5 6
Fig. 9.4 [For the item marked with *, see Page 51.] 50
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* Relationship between oscillation frequency fOSC, display clock frequency fCL and liquid crystal frame fFR Table 9.7 Item Built-in oscillator circuit used Built-in oscillator circuit not used fCL See p.33 fFR fCL (n+3)x16 fCL 1 (n = ) Duty (n+3)x16
External input (fCL)
(fFR indicates the cycle of rewriting one screen; it does not indicate FR signal cycle.) [Reference Matters for Items marked with *] *13 Indicate the current consumed by the IC only as well as by the internal power supply when the display is ON. fFR = 80Hz, VDD = VDD2, without n-line inversion, 1/8 bias, all internal power supply circuits are used. The internal oscillator circuit is not used. Current consumed by LCD panel capacity, wiring capacity, etc. is not included. This applies when no access is made from the MPU. *14 Heavy load means the display pattern status when the maximum current is consumed.
9.2 Characteristics of Temperature Sensor
Table 9.8 Item Output voltage Symbol VSVD2 Condition -35C 25C 80C *2 *3 *4 25C Specified value Min. Typ. Max. 1.430 1.475 1.519 1.164 1.200 1.236 0.907 0.935 0.963 -- -1.5 100 -- -4.70 -- -- 10 -- 1.5 -- 30 Unit V Applicable pin SVD2 *1
Output voltage temperature gradient Output voltage linearity Output voltage setup time Operating current
VGRA VL tSEN ISEN
mV/C % mS A
SVD2 SVD2 SVD2 VDD
[Reference Matters for Items marked with *] *1 Set the load capacity CL of the sensor voltage output pin SVD2 to 100pF or below and the load resistance RL to 1M or more. In order to get accurate output voltage values, do not provide with any current path between SVD2 and VSS.
SVD2 SVD2 CL RL
VSS
VSS
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S1D15714 Series
*2 Inclination of approximate straight line of Typ. output voltage between -35C and 80C . See Fig. 9.6. *3 Maximum deviation between output voltage curve and approximate straight line. See Fig. 9.6. When the output voltage difference between -35C and 85C is VSVD2, the difference between the approximate straight line and the output voltage linearity is DIFF, and the maximum value is DIFF (Max.), the output voltage linearity VL is expressed by the following formula
VL =
DIFF( MAX ) x 100 VSEN
Output voltage VSVD2 [V]
VDIFF Approximate line VDIFF VSEN = VSEN (-35C) - VSEN (85C) Output voltage
VDIFF
-50
-25
0
25 Temperature Ta [C]
50
75
100
Fig. 9.6
*4 The waiting time until the output voltage is stabilized and can be monitored after the temperature sensor ON command is input. Be sure to sample output voltages after a waiting time more than the specified one elapsed.
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10. TIMING CHARACTERISTICS
(1) System path read/write characteristics 1 (80 system MPU)
A0
tAW8
CS
tAH8
tCYC8
*1 WR, RD
tCCLR, tCCLW tCCHR, tCCHW
CS
*2 WR, RD
tf
tr
tDS8
D0 to D7 (Write)
tDH8
tACC8
D0 to D7 (Read)
tOH8
Fig. 10.1 Table 10.1 [VDD = 2.7V to 5.5V, Ta = -40 to +85C] Parameter Address hold time Address setup time System write cycle time System read cycle time Control LOW-pulse width (Write) Control LOW-pulse width (Read) Control HIGH-pulse width (Write) Control HIGH-pulse width (Read) Data setup time Data hold time RD access time Output disable time Signal A0 Symbol Condition -- -- -- Specified value Min. 0 0 500 7000 200 3000 200 200 200 30 -- 5 Max. -- -- -- -- -- -- -- -- -- -- 3500 200 Unit ns
tAH8 tAW8 WR tWCYC8 RD tRCYC8 WR tCCLW RD tCCLR WR tCCHW RD tCCHR D0 to D7 tDS8 tDH8 tACC8 tOH8
-- CL=100pF
*1. This is in case of making the access by WR and RD, setting the CS = LOW. *2. This is in case of making the access by CS, setting the WR, RD = LOW. *3. Input signal rise and fall time (tr, tf) must not exceed 15 ns. When the system cycle time is used at a high speed, it is specified by (tr + tf) (tCYC8 - tCCLW - tCCHW) or (tr + tf) (tCYC8 - tCCLR - tCCHR). *4. Timing is entirely specified with reference to 20% or 80% of VDD. *5. tCCLW and tCCLR are specified in terms of the overlapped period when CS is at LOW level and WR and RD are at LOW level. Rev. 1.0
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S1D15714 Series
(2) System path read/write characteristics 2 (68 system MPU)
A0 R/W
tAW6
CS *1
tAH6
tCYC6 tEWHR, tEWHW
E
tEWLR, tEWLW
CS *2 E
tf
tr
tDS6
D0 to D7 (Write)
tDH6
tACC6
D0 to D7 (Read)
tOH6
Fig. 10.2 Table 10.2 Parameter Address hold time Address setup time System write cycle time System read cycle time Data setup time Data hold time Access time Output disable time Enable HIGH-pulse width Read Write Enable LOW-pulse width Read Write Signal A0 Symbol [VDD = 2.7V to 5.5V, Ta = -40 to +85C] Condition -- -- -- CL=100pF -- -- Specified value Min. 20 0 500 7000 200 60 -- 5 3000 200 200 200 Max. -- -- -- -- -- -- 3500 200 -- -- -- -- Unit ns
tAH6 tAW6 E tWCYC6 tRCYC6 D0 to D7 tDS6 tDH6 tACC6 tOH6 E tEWHR tEWHW E tEWLR tEWLW
*1 This is in case of making the access by E, setting the CS = LOW. *2 This is in case of making the access by CS, setting the E = HIGH. *3 The rise time and the fall time (tr & tf) of the input signals should be set to 15ns or less. When it is necessary to use the system cycle time at high speed, the rise time and the fall time should be so set to conform to (tr+tf) (tCVC6-tEWLW-tEWHW) or (tr+tf) (tCYC6-tEWLR-tEWHR). *4 All the timing should basically be set to 20% and 80% of the "VDD". *5 tEWLW, tEWLR should be set to the overlapping zone where the CS is on the LOW level and where the E is on the HIGH level. 54
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(3) Serial interface
CS tCSS tCSH
tSAS A0
tSAH
tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH
Figure 10.3 Table 10.3 [VDD = 2.7V to 5.5V, Ta = -40 to +85C] Parameter Serial clock period SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal SCL Symbol Condition -- Specified value Min. 250 100 100 150 150 200 100 150 150 Max. -- -- -- -- -- -- -- -- -- Unit ns
A0 SI CS
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
-- -- --
*1. Input signal rise and fall time (tr, tf) must not exceed 15 ns. *2. Timing is entirely specified with reference to 20% or 80% of VDD.
Rev. 1.0
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S1D15714 Series
(4) Display control input/output timing
CL (OUT) tDFR FR tDF1,F2 F1, F2 tDSYNC SYNC
Fig. 10.4 Table 10.4 Output Timing [VDD = 2.7V to 5.5V, Ta = -40 to +85C] Parameter FR delay time F1, F2 delay time SYNC delay time Signal FR F1, F2 SYNC Symbol Condition CL = 50pF Specified value Min. -- -- -- Typ. 60 60 60 Max. 200 200 200 Unit ns ns ns
tDFR tDF1, tF2 tDSYNC
Table 10.5 Input Timing [VDD = 2.7V to 5.5V, Ta = -40 to +85C] Parameter FR delay time F1, F2 delay time SYNC delay time Low-level pulse width High-level pulse width Signal FR F1, F2 SYNC CL Symbol Condition Specified value Min. -1.0 -1.0 -1.0 1.0 1.0 Typ. -- -- -- -- -- Max. 1.0 1.0 1.0 -- -- Unit s s s s s
tDFR tDF1, tF2 tDSYNC tWLCL tWHCL
*1. Timing is entirely specified with reference to 20% or 80% of VDD.
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(5) Reset input timing
tRW
RES
tR
Internal state During resetting End of resetting
Fig. 10.5 Table 10.5 [VDD = 2.7V to 5.5V, Ta = -40 to +85C] Parameter Reset time Reset LOW pulse width Signal -- RES Symbol Condition -- Specified value Min. -- 1000 Typ. -- -- Max. 1000 -- Unit s
tR tRW
*1. Timing is entirely specified with reference to 20% or 80% of VDD.
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S1D15714 Series
11. MPU INTERFACE
The S1D15714 Series can be connected to the 80 series MPU and 68 series MPU. Use of a serial interface allows operation with a smaller number of signal lines. You can expand the display area using the S1D15714 Series as a multi-chip. In this case, the IC to be accesses can be selected individually by the chip select signal. After initialization by the RES pin, each input terminal of the S1D15714 Series must be placed under normal control. (1) 80 series MPU
VDD2 VDD VCC A0 A0 Decoder CS D0 to D7 RD WR RES VSS A1 to A7 IORQ VDD2 VDD C86
S1D15714 Series
MPU
D0 to D7 RD WR RES GND
P/S
RESET
VSS
Fig. 11.1 (2) 68 series MPU
VDD2 VDD VCC A0 A0 Decoder CS D0 to D7 E R/W RES VSS A1 to A15 VMA VDD2 VDD C86
S1D5714 Series
MPU
D0 to D7 E R/W RES GND
P/S
RESET
VSS
Fig. 11.2 (3) Serial interface
VDD2 VDD
VCC A0 A1 to A7
MPU
VDD2 A0 Decoder CS1 CS2 SI SCL RES VSS
VDD C86
S1D15714 Series
VDD or VSS
Port 1 Port 2 RES GND RESET
P/S
VSS
Fig. 11.3
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12. CONNECTION BETWEEN LCD DRIVERS
You can easily expand the liquid crystal display area using the S1D15714 Series as a multi-chip. In this case, use the same model (S1D15714/S1D15714) as the master and slave systems.
S1D15714 (Master) VDD VSS M/S CL FR DOF F1 F2 SYNC CLS V3 V2 V1 VC MV1 (VSS) MV2 (VSS) MV3 M/S CL FR DOF F1 F2 SYNC CLS V3 V2 V1 VC MV1 MV2 (VSS) MV3 (VSS) VDD S1D15714 (Slave)
Fig. 12 Master/slave connection example
Rev. 1.0
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S1D15714 Series
13. LCD PANEL WIRING
You can easily expand the liquid crystal display area using the S1D15714 Series as a multi-chip. In the case of multichip configuration, use the same models. (1) Single chip configuration example
168 x 65 Dots
COM
SEG S1D15714 Series Master
COM
Fig. 13.1 Single chip configuration example (2) Double chip configuration example
336 x 65 Dots
COM
SEG S1D15714 Series Master
SEG S1D15714 Series Slave
COM
Fig. 13.2 Double chip configuration example
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14. CAUTIONS
Cautions must be exercised on the following points when using this Development Specification: 1. This Development Specification is subject to change for engineering improvement. 2. This Development Specification does not guarantee execution of the industrial proprietary rights or other rights, or grant a license. Examples of applications described in This Development Specification are intended for your understanding of the Product. We are not responsible for any circuit problem or the like arising from the use of them. 3. Reproduction or copy of any part or whole of this Development Specification without permission of our company, or use thereof for other business purposes is strictly prohibited. For the use of the semi-conductor,cautions must be exercised on the following points: [Cautions against Light] The semiconductor will be subject to changes in characteristics when light is applied. If this IC is exposed to light, operation error may occur. To protect the IC against light, the following points should be noted regarding the substrate or product where this IC is mounted: (1) Designing and mounting must be provided to get a structure which ensures a sufficient resistance of the IC to light in practical use. (2) In the inspection process, environmental configuration must be provided to ensure a sufficient resistance of the IC to light. (3) Means must be taken to ensure resistance to light on all the surfaces, backs and sides of the IC
Rev. 1.0
EPSON
61
S1D15714 Series
ELECTRONIC DEVICES MARKETING DIVISION
Document code : 404780903 First issue October, 2003 Printed in Japan H A

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